The present invention relates to integrated circuitry, generally. More specifically, the present invention relates to methods and circuitry for reducing duty cycle distortion in differential delay lines used in integrated circuits.
Delay circuitry is commonly used in both analog and digital circuitry to delay signals as needed. In synchronous digital integrated circuitry, delay circuits are frequently used to precisely time signals. Delay circuitry can take many different forms. Some delay circuitry is designed to delay a single electrical signal.
A simple delay circuit may take the form of an inverter. Logic gates have delays associated with signals propagating through them. Where the logical state of the input signal must be preserved, a noninverting delay may be used. Alternatively, an even number of inverters may be used to preserve the logical state of the input signal. For example, a pair of series-connected inverters will delay an input signal for two gate delays. Any number of delay circuits may be cascaded in series to adjust, or design, for a particular delay duration.
Differential delay lines are used in synchronous digital integrated circuitry to delay a pair of electrical lines that may form a single signal of interest, e.g., a differential voltage. Cascading such differential delay lines for a desired delay is known in the art. However, there are problems associated with cascaded differential solid state delay lines. A differential solid state delay line, even though perfectly symmetrical at the schematic level, may suffer duty cycle distortion due to process and layout asymmetry. Additionally, duty cycle distortion may result in differential solid state delay lines from thermal gradients in the semiconductor device itself. Thus, there is a need in the art for methods and circuitry for reducing duty cycle distortion in differential delay lines used in integrated circuits.
The invention is a method and circuitry for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may be asymmetry associated with the physical layout of each individual delay line cell or stage, it is advantageous to cross-connect every x stage of an n-stage delay line.
A differential solid state delay line embodiment of the invention includes n differential delay cells wherein each of the differential delay cells includes a first input associated with a first output and a second input associated with a second output, wherein each of the n differential delay cells is connected in series to form the differential solid state delay line. The differential further includes an even number of the n differential delay cells being cross-connected, that is, a first output of a preceding one of the n differential delay cells is connected to a second input of a succeeding one of the n differential delay cells and a second output of the preceding one of the n differential delay cells is connected to a first input of the succeeding one of the differential delay cells.
A physical layout embodiment for a differential solid state delay line includes a plurality of individual differential delay cell layouts. Each of the individual differential delay cell layouts includes a first delay element physical layout having a first input and a first output and a second delay element physical layout having a second input and a second output. The first delay element physical layout may be asymmetrical relative to the second delay element physical layout. The plurality of individual differential delay cell layouts are abutted against one another. An even number of the abutted plurality of identical individual differential delay cell layouts are cross-connected. Cross-connected includes a first output from a preceding differential delay cell layout being connected to a second input of a succeeding differential delay cell layout, and a second output from the preceding differential delay cell layout being connected to a first input of the succeeding differential delay cell layout.
A method for reducing duty cycle distortion in differential delay lines in accordance with the present invention includes providing a plurality of differential solid state delay cells, wherein each of the plurality of differential solid state delay cells includes a first delay element having a first input coupled to a first output and a second delay element having a second input coupled to a second output. The first delay element is configured for delaying a first electrical signal input to the first input and for outputting the first electrical signal on the first output after a delay. The second delay element is configured for delaying a second electrical signal input to the second input and for outputting the second electrical signal on the second output after the delay. The plurality of differential solid state delay cells are cross-connecting in series an even number of times.
Another method embodiment for reducing duty cycle distortion in differential solid state delay lines includes generating a physical layout for a differential solid state delay circuit, the physical layout comprising a first delay element having a first input coupled to a first output and a second delay element with a second input coupled to a second output. The method further comprises assembling n stages of the physical layouts in series to form an outline of a differential solid state delay line and cross-connecting every x of the n stages, where x is an even integer.
Integrated circuit, electronic system and substrate embodiments including the differential solid state delay lines of the present invention are also disclosed.